Conventionally, in LSIs for RF band signal processing for mobile transmission, a filter circuit is used in which time constant is constituted not of a resistor as a discrete element and a capacitor but an operation transconductance amplifier (OTA) and a capacitor. Further, an integrated filter circuit having a general purpose property intensified by adding a cut-off frequency automatic adjustment circuit capable of automatic adjustment of the cut-off frequency is often employed in such a filter.
FIG. 5 shows a circuit diagram of a conventional filter circuit having a OTA and the cut-off frequency automatic adjustment circuit, used in an analog signal processing system. Referring to FIG. 5, the conventional filter circuit comprises OTA 101, OTA 102, capacitor 111 (capacitance C110), capacitor 112 (capacitance C120) and the cut-off frequency automatic adjustment circuit 200. A resistor 201 and a capacitor 202, which are external adjustment elements, are connected to the cut-off frequency automatic adjustment circuit 200.
In the OTA 101, a signal which is an object for filtering is inputted through a positive phase input terminal N100 and an output terminal thereof is connected to the positive phase input terminal of the OTA 102. An output terminal of the OTA 102 is connected to inverse phase input terminals of the OTA 101 and OTA 102. The OTA 101 and OTA 102 receive a signal outputted from the cut-off frequency automatic adjustment circuit 200 as a bias voltage. As a result, the OTA 101 and OTA 102 function as active loads of high input impedance and low output impedance.
The aforementioned capacitor 111 a terminal of which is grounded is connected to the output terminal of the OTA 101 and similarly the aforementioned capacitor 112 a terminal of which is grounded is connected to the output terminal of the OTA 102. Therefore, the filter section is constituted of the OTA 101 as an active load and the capacitor 111, and the OTA 102 as an active load and the capacitor 112, and a filtered signal can be outputted from the output terminal of the OTA 102. The frequency characteristic of this filter section is determined by the transconductances of the OTA 101 and OTA 102 and the capacitances of the capacitors 111, 112.
FIG. 6 is a circuit diagram common to the OTA 101 and OTA 102 and specifically indicates a differential amplification circuit section. The differential amplification circuit section shown in FIG. 6 comprises a P-channel type MOS transistor M10 for supplying a constant current to a pair of the differential transistors described below by inputting the bias voltage VB, a P-channel type MOS transistor M11 and a P-channel type MOS transistor M12, both acting as a pair of the differential transistors, and a N-channel type MOS transistor M13 and a N-channel type MOS transistor M14, both constituting a current mirror circuit functioning as an active load on the amplifier.
In this differential amplifying circuit section, a source of the MOS transistor M10 is connected to a power line which supplies a power voltage Vdd (high level voltage) and a gate thereof is connected to a terminal which supplies the bias voltage VB. In the MOS transistor M11 and MOS transistor M12, sources thereof are connected to each other, thereby constituting a pair of the differential transistor. Further, the sources of the MOS transistor M11 and MOS transistor M12 are connected to a drain of the MOS transistor M10, so that a current supplied through the MOS transistor M10 is supplied to the pair of the differential transistors constituted of the aforementioned MOS transistor M11 and MOS transistor M12.
A gate of the MOS transistor M11 is connected to an input node N190 of this differential amplification circuit section, namely to positive phase input terminals of the OTA 101 or OTA 102. Specifically, the gate of the MOS transistor M11 is connected to terminal N100 in the OTA 101 from where a signal which is an object for filtering is inputted. Further, a gate of the MOS transistor M12 is connected to the other input terminal N200 of the differential amplification circuit section, namely to inverse phase input terminal of the OTA 101 or OTA 102.
The gates of the MOS transistor M13 and MOS transistor M14 are connected to each other. The gate and drain of the MOS transistor M13 are connected to form a current mirror circuit. Sources of the MOS transistor M13 and MOS transistor M14 are connected to a line of grounding voltage Vss (low level voltage).
A difference between signals inputted into the input node N190 and input node N200 is amplified by this differential amplification circuit section. The amplified signal is outputted from the input node N210 connected to the drain of the MOS transistor M12 as an output signal. In the OTA 101 and OTA 102, because the respective inverse phase input terminals thereof corresponding to the input node N200 are connected to the output terminal of the OTA 102 a negative feedback loop with gain 1 is formed, thereby the OTA 101 and OTA 102 act as an active load.
On the other hand, FIG. 7 is a circuit diagram showing a structure of the cut-off frequency automatic adjustment circuit. The cut-off frequency automatic adjustment circuit 200 shown in FIG. 7 comprises an OTA 103 having the same structure as the aforementioned OTA 101 and 102, a comparator 240 and a sample hold circuit 300. The positive phase input terminal (+) of the OTA 103 is connected to a contact terminal of each of the analog switches 221, 222 and its inverse phase input terminal (-) is connected to an output node for dividing a voltage supplied from the power line by resistors 213, 214 connected in series, namely a joint between the resistors 213 and 214.
The other contact terminal of the analog switch 221 is connected to an output node for dividing a voltage supplied from the power line by the resistors 211, 212 connected in series, namely a joint between the resistors 211 and 212. The other contact terminal of the analog switch 222 is grounded.
The analog switch 221 inputs a clock CK1 into the N-channel type MOS transistor and a clock CK1i into the P-channel type MOS transistor as a change-over signal. The analog switch 222 inputs a clock CK1i into the N-channel type MOS transistor and a clock CK1 into the P-channel type MOS transistor side as a change-over signal.
The clock CK1 is a clock inputted from the clock input terminal N120 and the clock CK1i is a signal obtained by inverting the input of the clock CK1 by an inverter 251 as shown in the Figure. As a result, the analog switches 221, 222 are turned ON/OFF complementarily by the clocks CK1, CK1i.
Thus, in the OTA 103, a partial value supplied by the resistors 213, 214 is inputted into the inverse phase input terminal as a reference voltage and then, a signal changed over by the clock CK1 or either a partial voltage supplied by the resistors 213, 214 or grounding voltage is inputted into the positive phase input terminal and a signal based on a difference between these signals is outputted. Further, the OTA 103 receives a voltage determined by the sample hold circuit 300, which will be described later, and the resistor 201 and capacitor 202, which are the aforementioned external adjustment devices, as the bias voltage VB.
One of the terminals of a capacitor 231 (capacitance C100) and a contact terminal of the analog switch 223 are connected to an output terminal of the OTA 103. The other terminal of the capacitor 231 is grounded. The analog switch 223 inputs a clock CK2 into the N-channel type MOS transistor and a clock CK2i to the P-channel type MOS transistor as change-over signal.
The clock CK2 is a clock signal inputted from the clock input terminal N130 like the aforementioned clock CK1. The clock CK2i is a signal obtained by inverting the clock CK2 by an inverter 252 as shown in the Figure. Thus, the analog switch 223 is turned ON/OFF by these clocks CK2 and CK2i.
One of the terminals of a capacitor 232 (capacitance C200) and a positive phase input terminal of the comparator 240 are connected to the other contact terminal of the analog switch 223. The other terminal of the capacitor 232 is grounded. The same signal as a signal inputted into the inverse phase input terminal of the OTA 103, namely the voltage divided by the resistors 213, 214 is inputted into the inverse phase input terminal of the comparator 240.
Thus, due to ON/OFF of the analog switch 223, output voltage from the OTA 103 charged in the capacitor 231 can be held by the capacitor 232. This voltage held in the capacitor 232 is compared to the reference voltage determined by the aforementioned resistors 213, 214 by the comparator 240 and a result of comparison is outputted as a logical level.
The sample hold circuit 300 comprises a delay flip-flop 301, a P-channel type MOS transistor M31 and a N-channel type MOS transistor M32. The output of the comparator 240 is inputted into the D input of the delay flip-flop 301.
The aforementioned clock CK1 is used as a rising edge clock input (T input) of the delay flip-flop 301. QC output of the delay flip-flop 301 is inputted into gate of the MOS transistor M31 and gate of the MOS transistor M32. A signal having a level of inverted clock CK1 is inputted into T input of the delay flip-flop 301. The MOS transistor M31 and MOS transistor M32 constitute a complementary circuit and drains of these transistors function as a charge pump.
Drains of the MOS transistor M31 and MOS transistor M32 are connected to PDO terminal N300 and a source of the MOS transistor M31 is connected to a power line while a source of the MOS transistor M32 is grounded. The PDO terminal N200 is connected to the resistor 201 which is an external adjustment device as shown in FIG. 5 and this resistor is grounded through the capacitor 202. That is, a voltage outputted from the drains of the MOS transistor M31 and MOS transistor M32 is held (sample hold) by the capacitor 202.
VCOI terminal N310 shown in FIG. 7 is connected to an output terminal 220 of the cut-off frequency automatic adjustment circuit 200 and further connected to a joint between the resistor 201 and capacitor 202 as shown in FIG. 5. That is, the sample held voltage in the capacitor 202 is outputted from the cut-off frequency automatic adjustment circuit 200 and inputted as the bias voltage VB for the OTAs 101, 102 constituting the filter section, while it is inputted as the bias voltage VB for the OTA 103 within its own circuit.
Next, operation of the conventional filter circuit described above is described here. In this filter circuit, the cut-off frequency fc and quality factor Q are expressed as follows. ##EQU1##
where gm1 and gm2 indicate transconductances of the OTA 101 and OTA 102 and can be expressed as follows. EQU gm1=1/2.times.K'.times.W'/L'.times.(Vdd-VB-Vthp') EQU gm2=1/2.times.K".times.W"/L".times.(Vdd-VB-Vthp")
In the above expression, K' indicates mobility, W'/L' indicates a transistor size, Vdd indicates a voltage of the source of and Vthp' indicates a threshold of the MOS transistor M10 in OTA 101. Similarly K" indicates mobility, W"/L" indicates transistor size and Vthp" indicates a threshold of the MOS transistor M10 in the OTA 102
The cut-off frequency of the filter circuit is determined by these gm1, gm2, C110 and C120 as described above and particularly because the transconductances gm1, gm2 use the bias voltage VB as one of the parameters, by changing this bias voltage VB, a desired cut-off frequency can be set up. The cut-off frequency automatic adjustment circuit 200 enables to change the cut-off frequency by inputting the bias voltage VB into the OTAs 101 and 102 corresponding to the frequencies of the clocks CK1 and CK2.
Next, operation of the cut-off frequency automatic adjustment circuit 200 will be described. FIG. 8A to FIG. 8F are timing chart that explain the operation of the cut-off frequency automatic adjustment circuit 200. In FIG. 7, the partial value determined by the resistors 211, 212 and the partial value determined by the resistors 213, 214 are set up such that a voltage of the OTA 103 outputted when the clock CK1 has logical level "H" is a value near the logical level "H", and if the voltage held in the capacitor 232 exceeds the aforementioned reference voltage, the comparator 240 outputs the logical level "H".
As shown in FIG. 8A, if the clock CK1 has a logical level "H" at time T0, then the analog switch 221 is turned ON while the analog switch 222 is turned OFF. As shown in FIG. 8B, the partial value determined by the resistors 211, 212 is inputted into the positive phase input terminal of the OTA 103 (point C in FIG. 7). As a result, a positive voltage is outputted from the OTA 103 and charged in the capacitor 231 as shown in FIG. 8D (point D in FIG. 7).
As shown in FIG. 8C, if the clock CK2 has a logical level "H" at time T0, the analog switch 223 is turned ON, so that a voltage outputted from the OTA 103 is charged in the capacitor 232 as shown in the FIG. 8E (point E in FIG. 7). Because the voltage at the point E inputted into the positive phase input terminal of the comparator 240 has not reached the reference voltage to be inputted into the inverse phase input terminal, the logical level "L" is outputted as shown in FIG. 8F (point F in FIG. 7).
Further, at time T0, the grounding voltage or a holding voltage of the capacitor 232 not sufficiently charged is inputted into the positive phase input terminal of the comparator 240 and the logical level "H" is inputted into the D input of the delay flip-flop 301. However, because the clock CK1 has the logical level "H", the logical level "L" is inputted into T input and an inversion level "L" of the logical level "H" which is a holding voltage of D input is outputted from the QC output.
Consequently, the MOS transistor M31 is turned ON and the MOS transistor M32 is turned OFF, so that a power voltage is outputted to the PDO terminal. As a result, the capacitor 202 shown in FIG. 5 is charged.
Then, at time T1, only the clock CK2 is turned to the logical level "L" so that the analog switch 223 is turned OFF, an output voltage of the OTA 103 is held by the capacitor 232 as shown in FIG. 8E. Because this output voltage exceeds the reference voltage of the comparator 240, the logical level "H" is outputted from the comparator 240 as shown in FIG. 8F.
A voltage having the logical level "H" outputted from the comparator 240 is inputted into D input of the delay flip-flop 301. Because at this time, the clock CK1 has the logical level "H", inverted level "L" of the logical level "H" is inputted into T input. Then, the logical level "H" is outputted from the QC output, so that the MOS transistor M31 is turned OFF and the MOS transistor M32 is turned ON, and a grounding voltage is outputted to the PDO terminal. As a result, a voltage held by the capacitor 202 shown in FIG. 5 is discharged. This means that the voltage charged in the capacitor 202 till this time becomes a voltage to be outputted as the bias voltage VB.
If at time T2, the clock CK1 has a logical level "L", the analog switch 221 is turned OFF and the analog switch 222 is turned ON. As a result, an output of the OTA 101 becomes a grounding voltage or negative voltage, so that a potential at the point D in FIG. 7 gradually drops due to discharging of the capacitor 231 as shown in FIG. 8D.
Because the clock CK2 still has the logical level "L", the analog switch 223 is kept OFF and a voltage held by the capacitor 232 is inputted into the positive phase input terminal of the comparator 240. Therefore, a voltage to be outputted from the PDO terminal is maintained at the grounding voltage.
At time T4, when the clock CK1 and clock CK2 once more become the logical level "H", the aforementioned operation is repeated. As a result, in the cut-off frequency automatic adjustment circuit 200, a maximum voltage to be charged or discharged by the capacitor 202 can be changed by the frequencies of the clocks CK1, CK2 and this voltage can be inputted into the OTAs 101, 102 as the bias voltage VB.
Further, the cut-off frequency automatic adjustment circuit 200 also functions as a circuit capable of absorbing a deflection of the capacitors C110, C120 and a deflection of the threshold Vthp of the MOS transistor M10.
However, in the conventional filter circuit described above, because the adjustment range of the cut-off frequency is determined by only the frequencies of the clocks CK1, CK2 inputted into the cut-off frequency automatic adjustment circuit 200, there are problems that the adjustment range is relatively narrow and a demand for adjustment of the cut-off frequency in a wide range cannot be met.